-- Rejestr 8-bitowy 2-wejsciowy/2-wyjsciowy
-- Wejscia danych: DATAIN1[7..0] DATAIN2[7..0]
-- Wyjscia danych: DATAOUT1[7..0] DATAOUT2[7..0]
-- Wejscia sterujace:
-- IE1# IE2# (input enable)
-- OE1# OE2# (output enable)

library IEEE;
use IEEE.Std_Logic_1164.all;

entity DOUBLEREG8 is
  generic (delay : time := 5 ns);
  port (IE1, OE1, IE2, OE2 : in std_logic;
        DATAIN1, DATAIN2   : in std_logic_vector(7 downto 0);
        DATAOUT1, DATAOUT2  : out std_logic_vector(7 downto 0));
end entity DOUBLEREG8;

architecture DOUBLEREG8_arch of DOUBLEREG8 is
begin
  process(IE1, OE1, IE2, OE2, DATAIN1, DATAIN2)
    variable buf : std_logic_vector(7 downto 0);
  begin
    if (IE1 = '0' and IE2 /= '0') then
      buf := DATAIN1;
    elsif (IE2 = '0' and IE1 /= '0') then
      buf := DATAIN2;
    end if;
    if (OE1 = '0') then
      DATAOUT1 <= buf after delay;
      else DATAOUT1 <= "ZZZZZZZZ" after delay;
    end if;
    if (OE2 = '0') then
      DATAOUT2 <= buf after delay;
      else DATAOUT2 <= "ZZZZZZZZ" after delay;
    end if;
  end process;
end architecture DOUBLEREG8_arch;
